View R1EX25008ASA00G_7200711.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary datasheet R1EX25008ASA00G/r1ex25008ata00g r1ex25016asa00g/r1ex25016ata00g serial peripheral interface 8k eeprom (1024-word ? 8-bit) 16k eeprom (2048-word ? 8-bit) 105c spi-bus eeprom r10ds0083ej0100 rev.1.00 oct. 02, 2012 description r1ex25xxx series is the serial pe ripheral interface compatible (spi) eeprom (electrically erasable and programmable rom). r1ex25xxxg series improves the write/e rase endurance in addition to suitable for the high temperature industrial applica tion that makes the best use of the feature of advanced monos memory cell structure. features ? single supply: 1.8 v to 5.5 v ? serial peripheral interface compatible (spi bus) ? spi mode 0 (0,0), 3 (1,1) ? clock frequency: 5 mhz (2.5 v to 5.5 v), 3 mhz (1.8 v to 5.5 v) ? power dissipation: ? standby: 2 ? a (max) ? active (read): 2.5 ma (max) ? active (write): 3 ma (max) ? automatic page write: 32-byte/page ? write cycle time: 5 ms ? endurance: 1,000k cycles @85 ? c / 200k cycles @105 ? c ? data retention: 20 years ? small size packages: sop-8pin, tssop-8pin ? shipping tape and reel ? tssop 8-pin: 3,000 ic/reel ? sop 8-pin: 2,500 ic/reel ? temperature range: ? 40 to +105 ? c ? lead free products. ? halogen free products. preliminary: the specifications of this device are subject to change without notice. please contact your nearest renesas electronics? sales dept. regarding specifications. r10ds0083ej0100 rev.1.00 page 1 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary ordering information orderable part numbers internal organization package shipping tape and reel R1EX25008ASA00G#u0 8k bit (1024 ? 8-bit) r1ex25016asa00g#u0 16k bit (2048 ? 8-bit) 150 mil 8-pin plastic sop prsp0008df-b (fp-8dbv) lead free, halogen free 2,500 ic/reel r1ex25008ata00g#u0 8k bit (1024 ? 8-bit) r1ex25016ata00g#u0 16k bit (2048 ? 8-bit) 8-pin plastic tssop ptsp0008jc-b (ttp-8dav) lead free, halogen free 3,000 ic/reel pin arrangement 8-pin sop/tssop (top view) 1 2 3 4 8 7 6 5 v cc c d q v ss pin description pin name function c serial clock d serial data input q serial data output s chip select w write protect hold hold v cc supply voltage v ss ground r10ds0083ej0100 rev.1.00 page 2 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary block diagram high voltage generator memory array y-select & sense amp. serial-parallel converter address generator control logic y decoder x decoder v cc v ss s w c h old d q voltage detector absolute maximum ratings parameter symbol value unit supply voltage relative to v ss v cc ? 0.6 to +7.0 v input voltage relative to v ss v in ? 0.5 * 2 to +7.0 * 3 v operating temperature range * 1 topr ? 40 to +105 ?c storage temperature range tstg ? 55 to +125 ?c notes: 1. including electrical c haracteristics and data retention. 2. v in (min): ? 3.0 v for pulse width ? 50 ns. dc operating conditions parameter symbol min typ max unit v cc 1.8 ?? 5.5 v supply voltage v ss 0 0 0 v v ih v cc ? 0.7 ? v cc ? 0.5 * 2 v input voltage v il ? 0.3 * 1 ? v cc ? 0.3 v operating temperat ure range topr ? 40 ? +105 ?c notes: 1. v in (min): ? 1.0 v for pulse width ? 50 ns. 2. v in (max): v cc + 1.0 v for pulse width ? 50 ns. capacitance (ta = +25 ? c, f = 1 mhz) parameter symbol min typ max unit test conditions input capacitance (d, c, s, w, hold) cin * 1 ? ? 6.0 pf vin = 0 v output capacitance (q) c i/o * 1 ? ? 8.0 pf vout = 0 v note: 1. not 100 ? tested. memory cell characteristics (v cc = 1.8 v to 5.5 v) ta=85 ?c ta=105?c notes endurance 1,000k cycles min. 200k cycles min. 1 data retention 20 years min. 20 years min. 1 note: 1. not 100 ? tested. r10ds0083ej0100 rev.1.00 page 3 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary r10ds0083ej0100 rev.1.00 page 4 of 20 oct. 02, 2012 dc characteristics parameter symbol min typ max unit test conditions input leakage current i li ? ? 2 ? a v cc = 5.5 v, v in = 0 to 5.5 v (s, d, c, hold, w) output leakage current i lo ? ? 2 ? a v cc = 5.5 v, v out = 0 to 5.5 v (q) v cc current standby i sb ? 0.5 ? ? a v in = v ss or v cc , v cc = 3.6 v ? ? 2 ? a v in = v ss or v cc , v cc = 5.5 v active i cc1 ? 0.7 2 ma v cc = 3.6 v, read at 5 mhz v in = v cc ? 0.1/v cc ? 0.9 q = open ? ? 2.5 ma v cc = 5.5 v, read at 5 mhz v in = v cc ? 0.1/v cc ? 0.9 q = open i cc2 ? 1.2 2 ma v cc = 3.6 v, write at 5 mhz v in = v cc ? 0.1/v cc ? 0.9 ? ? 3 ma v cc = 5.5 v, write at 5 mhz v in = v cc ? 0.1/v cc ? 0.9 output voltage v ol1 ? ? 0.4 v v cc = 5.5 v, i ol = 2 ma v ol2 ? ? 0.4 v v cc = 2.5 v, i ol = 1.5 ma v oh1 v cc ? 0.8 ? ? v v cc = 5.5 v, i oh = ? 2 ma v oh2 v cc ? 0.8 ? ? v v cc = 2.5 v, i oh = ? 0.4 ma
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary r10ds0083ej0100 rev.1.00 page 5 of 20 oct. 02, 2012 ac characteristics test conditions ? input pules levels: ? v il = v cc ? ? v ih = v cc ? ? input rise and fall time: ? ? input and output timing reference levels: v cc ? ? ? output reference levels: v cc ? ? output load: 100 pf (ta = ? ? parameter symbol alt min max unit notes clock frequency f c f sck ? 5 mhz s active setup time t slch t css1 90 ? ns s not active setup time t shch t css2 90 ? ns s deselect time t shsl t cs 90 ? ns s active hold time t chsh t csh 90 ? ns s not active hold time t chsl ? 90 ? ns clock high time t ch t clh 90 ? ns 1 clock low time t cl t cll 90 ? ns 1 clock rise time t clch t rc ? 1 ? s 2 clock fall time t chcl t fc ? 1 ? s 2 data in setup time t dvch t dsu 20 ? ns data in hold time t chdx t dh 30 ? ns clock low hold time after hold not active t hhch ? 70 ? ns clock low hold time after hold active t hlch ? 40 ? ns clock high setup time before hold active t chhl ? 60 ? ns clock high setup time before hold not active t chhh ? 60 ? ns output disable time t shqz t dis ? 100 ns 2 clock low to output valid t clqv t v ? 70 ns output hold time t clqx t ho 0 ? ns output rise time t qlqh t ro ? 50 ns 2 output fall time t qhql t fo ? 50 ns 2 hold high to output low-z t hhqx t lz ? 50 ns 2 hold low to output high-z t hlqz t hz ? 100 ns 2 write time t w t wc ? 5 ms notes: 1. t ch ? t cl ? 1/f c 2. not 100 ? tested.
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary r10ds0083ej0100 rev.1.00 page 6 of 20 oct. 02, 2012 (ta = ? 40 to +105 ? c, v cc = 1.8 v to 5.5 v) parameter symbol alt min max unit notes clock frequency f c f sck ? 3 mhz s active setup time t slch t css1 100 ? ns s not active setup time t shch t css2 100 ? ns s deselect time t shsl t cs 150 ? ns s active hold time t chsh t csh 100 ? ns s not active hold time t chsl ? 100 ? ns clock high time t ch t clh 150 ? ns 1 clock low time t cl t cll 150 ? ns 1 clock rise time t clch t rc ? 1 ? s 2 clock fall time t chcl t fc ? 1 ? s 2 data in setup time t dvch t dsu 30 ? ns data in hold time t chdx t dh 50 ? ns clock low hold time after hold not active t hhch ? 140 ? ns clock low hold time after hold active t hlch ? 90 ? ns clock high setup time before hold active t chhl ? 120 ? ns clock high setup time before hold not active t chhh ? 120 ? ns output disable time t shqz t dis ? 200 ns 2 clock low to output valid t clqv t v ? 120 ns output hold time t clqx t ho 0 ? ns output rise time t qlqh t ro ? 100 ns 2 output fall time t qhql t fo ? 100 ns 2 hold high to output low-z t hhqx t lz ? 100 ns 2 hold low to output high-z t hlqz t hz ? 100 ns 2 write time t w t wc ? 5 ms notes: 1. t ch ? t cl ? 1/f c 2. not 100 ? tested.
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary timing waveforms serial input timing c t chsl t slch t chdx t clch t chcl t shch t chsh t shsl t dvch msb in lsb in d q high impedance hold timing t chhl c d q t hlch t chhh t hlqz t hhqx t hhch output timing c d q lsb out addr lsb in t qlqh t qhql t shqz t ch t cl t clqv t clqx t clqv t clqx r10ds0083ej0100 rev.1.00 page 7 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary r10ds0083ej0100 rev.1.00 page 8 of 20 oct. 02, 2012 pin function serial data output (q) this output signal is used to transfer data serially out of the device. data is shifted out on the falling edge of serial clock (c). serial data input (d) this input signal is use d to transfer data serially into the device. it receives in structions, addresses, and the data to be written. values are latched on the rising edge of serial clock (c). serial clock (c) th is input signal provides the timing of the serial interface. in structions, addresses, or data present at serial data input (d) are latched on the rising edge of serial clock (c). data on serial data output (q) changes after the falling edge of serial clock (c). chip select (s) w hen this input signal is high, the device is deselected and serial data output (q) is at high impedance. unless an internal write cycle is in progress, the device will be in the standby mode. driving chip select ( s ) low enables the device, placing it in the active power mode. after power-up, a falling edge on chip select ( s ) is required prior to the start of any instruction. hold (hold) the hold ( hold ) sign al is used to pause any serial communications with the device without deselecting the device. during the hold condition, the serial data output (q) is high im pedance, and serial data input (d) and serial clock (c) are don?t care. to start the hold condition, the de vice must be selected, with chip select ( s ) driven low. write protect (w) the m ain purpose of this input signal is to freeze the size of the area of memory that is protected against write instructions (as specified by the values in the bp1 and bp0 bits of the status register). this pin must be driven either high or low, and must be stable during all write operations.
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary functional description status register the following figure shows the status re gister format. the status register contains a number of status and control bits that can be read or set (as ap propriate) by speci fic instructions. status register format srwd 0 0 0 bp1 bp0 wel wip b7 status register write disable block protect bits write enable latch bits write in progress bits b0 wip bit: the write in progress (wip) bit indicates whether th e memory is busy with a write or write status register cycle. wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. bp1, bp0 bits: the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. srwd bit: the status register write disable (srwd) bit is operated in conjunction with the write protect ( w ) signal. the status register write disabl e (srwd) bit and write protect ( w ) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srwd, bp1, bp0) become read-only bits. instructions each i nstruction starts with a single-byte code, as summarized in the following table. if an invalid instruction is sent (one not contained in the following table) , the device automatically deselects itself. instruction set instruction description instruction format wren write enable 0000 0110 wrdi write disable 0000 0100 rdsr read status register 0000 0101 wrsr write status register 0000 0001 read read from memory array 0000 0011 write write to memory array 0000 0010 r10ds0083ej0100 rev.1.00 page 9 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary write enable (wren): the write enable latch (wel) bit must be set prior to each write and wrsr instruction. the only way to do this is to send a write enable instruction to the device. as shown in the following figure, to send th is instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte ar e shifted in, on serial data input (d). the device then enters a wait state. it waits for the de vice to be deselected, by chip select ( s ) being driven high. write enable (wren) sequence c d q instruction 0123456 high-z v ih v il v ih v il v ih v il v ih v il 7 r10ds0083ej0100 rev.1.00 page 10 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary write disable (wrdi): one way of resetting the write enable latch (wel) bit is to send a write disable instruction to the device. as shown in the following figure, to send this instruction to the device, chip select ( s ) is driven low, and the bits of the instruction byte are shifted in, on serial data input (d). the device then enters a wait state. it waits fo r the device to be deselected, by chip select ( s ) being driven high. the write enable latch (wel) bit, in fact, beco mes reset by any of the following events: ? power-up ? wrdi instruction execution ? wrsr instruction completion ? write instruction completion write disable (wrdi) sequence c d q instruction 1 0 234567 high-z v ih v il v ih v il v ih v il v ih v il r10ds0083ej0100 rev.1.00 page 11 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary read status register (rdsr): the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a write or write status register cycle is in progress. when on e of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in the following figure. read status register (rdsr) sequence c d q status register out 01234567 0123456 77 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il the status and control bits of th e status register are as follows: wip bit: the write in progress (wip) bit indicates whether the me mory is busy with a write or write status register cycle. when set to 1, such a cycl e is in progress. when reset to 0, no such cycles are in progress. wel bit: the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1, the internal write enable latch is set. when set to 0, th e internal write enable latch is reset and no write or write status register instructions are accepted. bp1, bp0 bits: the block protect (bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against write instructions. these bits are written w ith the write status register (wrsr) instruction. when one or both of the block protect (bp1, bp0) bits are set to 1, the relevant memory area (as defined in the status register format table) becomes protected against write (write) instructions. the block protect (bp1, bp0) bits can be written provided that the hardware protected mode has not been set. srwd bit: the status register write disable (srwd) bit is operated in conjunction with the write protect ( w ) signal. the status register write disabl e (srwd) bit and write protect ( w ) signal allows the device to be put in the hardware protected mode (when the status register write disable (srwd) bit is set to 1, and write protect ( w ) signal is driven low). in this mode, the non-volatile bits of the status regi ster (srwd, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. r10ds0083ej0100 rev.1.00 page 12 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary write status register (wrsr): the write status register (wrsr) instruction allows new valu es to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the instruction sequence is shown in the following figure. the write status register (wrsr) instruction has no effect on b6, b5, b4, b1 and b0 of the status register. b6, b5 and b4 ar e always read as 0. chip select ( s ) must be driven high after the rising edge of serial clock (c) that latches in the eighth bit of the data byte, and before the next rising edge of serial clock (c). otherwise, the write status register (wrsr) instruc tion is not executed. as soon as chip select ( s ) is driven high, the self-timed write status regist er cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check th e value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status regi ster cycle, and is 0 when it is completed. when the cycle is completed, write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in the status register format table. the write status register (wrsr) instru ction also allows the user to set or reset the status register write disable (srwd) bit in accordance w ith the write protect ( w ) signal. the status register write disable (srwd) bit and write protect ( w ) signal allows the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hardware protected mode (hpm) is entered. the contents of the status register write disable (srwd) and block protect (bp1, bp0) bits are frozen at their current values just before the start of the execution of the write st atus register (wrsr) instruction. the new, updated values take effect at the moment of completion of the execu tion of write status register (wrsr) instruction. write status register (wrsr) sequence c d q status register in msb 01234567 01234567 8 9 10 11 12 13 14 15 high-z v ih v il v ih v il v ih v il v ih v il r10ds0083ej0100 rev.1.00 page 13 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary read from memory array (read): as shown in the following figure, to send th is instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte and the address bytes are then shifted in, on serial data input (d). the addresses are loaded into an internal address register, and the byte of data at that address is shifted out, on serial data output (q). if chip select ( s ) continues to be driven low, the in ternal address register is automati cally incremented, and the byte of data at the new address is shifted out. when the highest address is reached, the address counter rolls over to zero, allo wing the read cycle to be continued indefinitely. the whole memory can, therefore, be read with a single read instruction. the read cycle is terminated by driving chip select ( s ) high. the rising edge of the chip select ( s ) signal can occur at any time during the cycle. the addressed first byte can be any byte within any page. the instruction is not accepted, and is not executed, if a write cycle is currently in progress. read from memory array (read) sequence c d q 16-bit address data out 2 data out 1 01234567 a0a1a2a3 a13a14a15 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 high-z v ih v il v ih v il v ih v il v ih v il 012 3 4 5 6 77 instruction note: 1. depending on the memory size, as shown in the following table, the most significant address bits are don?t care. address range bits device r1ex25016a r1ex25008a address bits a10 to a0 a9 to a0 notes: 1. b15-b11 are don?t care on the r1ex25016a 2. b15-b10 are don?t care on the r1ex25008a r10ds0083ej0100 rev.1.00 page 14 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary write to memory array (write): as shown in the following figure, to send th is instruction to the device, chip select ( s ) is first driven low. the bits of the instruction byte, address byte, and at least one data byte are then shifted in, on serial data input (d). the instruction is terminated by driving chip select ( s ) high at a byte boundary of the input data. in the case of the following figure, this occurs after the eighth bit of the data byte has been latched in, indicating that the instruction is being used to write a single byte. the self-timed write cycle starts, and continues for a period t wc (as specified in ac characteristics). at the end of the cycle, th e write in progress (wip) bit is reset to 0. if, though, chip select ( s ) continues to be driven low, as shown in the follo wing figure, the next byte of the input data is shifted in, so that more than a single byte, starting from the given address towards the end of the same page, can be written in a single internal write cycle. each time a new data byte is shifted in, the least significant b its of the internal address count er are incremented. if the number of data bytes sent to the device exceeds the page boundary, the internal address counter rolls over to the beginning of the page, and the previous data there are overwritten with the incoming data. (the page size of these device is 32 bytes). the instruction is not accepted, and is no t executed, under the following conditions: ? if the write enable latch (wel) bit has not been set to 1 (by executing a write enable instruction just before) ? if a write cycle is already in progress ? if the addressed page is in the region protected by the block protect (bp1 and bp0) bits. byte write (write) sequence (1 byte) c d q 16-bit address data byte 1 01234567 0123 a13a14a15 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction note: 1. depending on the memory size, as shown in addre ss range bits table, the most significant address bits are don?t care. r10ds0083ej0100 rev.1.00 page 15 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary byte write (write) sequence (page) c d q 16-bit address data byte 1 01234567 0123 a13a14a15 8 9 10 20 21 22 23 24 25 26 27 28 29 30 31 high-z v ih v il v ih v il v ih v il v ih v il 4 5 6 7 a0 a1 a2 a3 instruction c d q data byte 3 data byte n 32 33 34 35 36 37 38 39 7 40 41 42 43 44 45 46 47 high-z v ih v il v ih v il v ih v il 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 6 5 4 3 2 1 0 data byte 2 note: 1. depending on the memory size, as shown in addre ss range bits table, the most significant address bits are don?t care. r10ds0083ej0100 rev.1.00 page 16 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary r10ds0083ej0100 rev.1.00 page 17 of 20 oct. 02, 2012 data protect the protection features of the device are summarized in the fo llowing table. when the status register write disable (srwd) bit of the status register is 0 (its initial delivery state), it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction, regardless weather write protect ( w ) is driven high or low. when the status register write disable (srwd) bit of the stat us register is set to 1, two cases need to be considered, depending on the state of write protect ( w ): ? if write protect ( w ) is driven high, it is possible to write to the status register provided that the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. ? if write protect ( w ) is driven low, it is not possible to write to th e status register even if the write enable latch (wel) bit has previously been set by a write enable (wren) instruction. (attempts to write to the status register are rejected, and are not accept ed for execution). as a consequence, all the data bytes in the memory area that are software protected (spm) by the block protect (bp1, bp0) bits of the status register, are also hardware protected against data modification. regardless of the order of the two events, the hardware protected mode (hpm) can be entered: ? by setting the status register write disable (srwd) bit after driving write protect ( w ) low. ? by driving write protect ( w ) low after setting the status regi ster write disable (srwd) bit. the only way to exit the hardware protected mode (hpm) once entered is to pull write protect ( w ) high. if write protect ( w ) is permanently tied high, the hardware protected mode (hpm) can never be activated, and only the software protected mode (spm), using the block protect (bp1, bp0) bits of the status register, can be used. write protected block size status register bits array addresses protected bp1 bp0 protected blocks r1ex25016a r1ex25008a 0 0 none none none 0 1 upper quarter 600h ? 7ffh 300h ? 3ffh 1 0 upper half 400h ? 7ffh 200h ? 3ffh 1 1 whole memory 000h ? 7ffh 000h ? 3ffh protection modes memory protect w signal srwd bit mode write protection of the status register protected area * 1 unprotected area * 1 1 0 software protected (spm) status register is writable (if the wren) instruction has set the wel bit). the values in the bp1 and bp0 bits can be changed. write protected ready to accept write instructions 0 0 1 1 0 1 hardware protected (hpm) status register is hardware write protected. the values in the bp1 and bp0 bits cannot be changed. write protected ready to accept write instructions note: 1. as defined by the values in the block protected ( bp1, bp0) bits of the status register, as shown in the write protected block size table.
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary hold condition the hold ( hold ) signal is used to pause any serial communicatio ns with the device without resetting the clocking sequence. during the hold condition, the serial data output (q) is high im pedance, and serial data input (d) and serial clock (c) are don?t care. to enter the hold condition, the device mu st be selected, with chip select ( s ) low. normally, the device is kept selected, for the whole duration of the hold condition. deselecting the device while it is in the hold condition, has the effect of resetting the state of the device, and this mechanism can be used if it is required to reset any processes that had been in progress. the hold condition starts when the hold ( hold ) signal is driven low at the same time as serial clock (c) already being low (as shown in the following figure). the hold condition ends when the hold ( hold ) signal is driven high at the same time as serial clock (c) already being low. the following figure also shows what happens if the rising and falling edges are not timed to coincide with serial clock (c) being low. hold condition activation c hold status hold status notes data protection at v cc on/off when v cc is turned on or off, noise on s inputs generated by external circuits (c pu, etc) may act as a trigger and turn the eeprom to unintentional program mode. to prevent this unintentional programming, this eeprom have a power on reset function. be careful of the noti ces described below in order for the power on reset function to operate correctly. ? s should be fixed to v cc during v cc on/off. low to high or high to low transition during v cc on/off may cause the trigger for the unintentional programming. ? v cc should be turned on/o ff after the eeprom is placed in a standby state. ? v cc should be turned on from the ground level (v ss ) in order for the eeprom not to enter the unintentional programming mode. ? v cc turn on rate should be slower than 2 ? s/v. ? when wrsr or write instruction is executed before v cc turns off, v cc should be turned off after waiting write cycle time (t w ). power source noise countermeasures in order to suppress power-source-noise which causes malfunction of the device, it is recommended to put 0.1uf bypass-capacitor (such as a monolithic ceramic capacitor wh ich has good high-frequency characteristics) between v cc and v ss , and shorten the wiring leng th between the capacitor and v cc /v ss terminals as much as possible. r10ds0083ej0100 rev.1.00 page 18 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary package dimensions R1EX25008ASA00G/r1ex25016asa00g (prsp00 08df-b / previous code: fp-8dbv) prsp0008df-b p-sop8-3.9x4.89-1.27 a l e c b d e a b c x y h z l 2 1 1 e 1 mass[typ.] 0.08g 4.89 1.06 0.25 0 8 6.02 0.15 0.20 0.25 0.45 0.102 0.14 0.254 3.90 0.406 0.60 0.889 1.73 reference symbol dimension in millimeters min nom max previous code jeita package code renesas code fp-8dbv 5.15 1 a p 0.35 0.40 6.20 5.84 1.27 0.10 0.69 index mark e 1 y xm p *3 *2 *1 f 4 85 d e h a z b p terminal cross section ( ni/pd/au plating ) b c detail f 1 1 l l a note) 1. dimensions"*1 (nom)"and"*2" do not include mold flash. 2. dimension"*3"does not include trim offset. e r10ds0083ej0100 rev.1.00 page 19 of 20 oct. 02, 2012
R1EX25008ASA00G/r1ex25008ata00g/r1ex25016asa00g/r1ex25016ata00g preliminary r1ex25008ata00g/r1ex25016ata00g (ptsp 0008jc-b / previous code: ttp-8dav) ptsp0008jc-b p-tssop8-4.4x3-0.65 a l e c b d e a b c x y h z l 2 1 1 e 1 mass[typ.] 0.034g 3.00 1.00 0.13 0 8 6.40 0.10 0.15 0.20 0.25 0.03 0.07 0.10 4.40 0.40 0.50 0.60 1.10 reference symbol dimension in millimeters min nom max previous code jeita package code renesas code ttp-8dav 3.30 1 a p 0.15 0.20 6.60 6.20 0.65 0.10 0.805 *1 85 e *2 index mark 14 *3 p mx y f a d e h z b detail f 1 1 a l l p terminal cross section ( ni/pd/au plating ) c b note) 1. dimensions"*1 (nom)"and"*2" do not include mold flash. 2. dimension"*3"does not include trim offset. e r10ds0083ej0100 rev.1.00 page 20 of 20 oct. 02, 2012
all trademarks and registered trademarks are t he property of their respective owners. c - 1 revision history r1ex2500 8asa00g/r1ex25008ata00g/ ///////// ///////// r1ex25016asa00g/r1ex2501 6ata00g data sheet description rev. date page summary 0.01 may. 16, 2011 ? initial issue 1.00 oct. 02, 2012 ? dlete preliminary 1 data retention: change 10 years to 20 years. 2 ordering information: change #s0 to #u0. addition of halogen free. memory cell characteristics: data retention: change 10 years to 20 years. 3 block diagram: addition of voltage detector. addition dc characteristics i sb =0.5 ? a(typ)@3.6v, i cc1 =0.7ma(typ)@3.6v, , i cc2 =1.2ma(typ)@3.6v 18 addition these items for notes (power source noise countermeasures)
notice 1. all information included in this document is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas electronics products listed herein, please confirm the latest product information with a renesas electronics sales office. also, please pay regular and careful attention to additional and different information to be disclosed by renesas electronics such as that disclosed through our website. 2. renesas electronics does not assume any liability for infringement of patents, copyrights, or other intellectual property rights of third parties by or arising from the use of renesas electronics products or technical information described in this document. no license, express, implied or otherwise, is granted hereby under any patents, copyrights or other intellectual property rights of renesas electronics or others. 3. you should not alter, modify, copy, or otherwise misappropriate any renesas electronics product, whether in whole or in part . 4. descriptions of circuits, software and other related information in this document are provided only to illustrate the operation of semiconductor products and application examples. you are fully responsible for the incorporation of these circuits, software, and information in the design of your equipment. renesas electronics assumes no responsibility for any losses incurred by you or third parties arising from the use of these circuits, software, or information. 5. when exporting the products or technology described in this document, you should comply with the applicable export control laws and regulations and follow the procedures required by such laws and regulations. you should not use renesas electronics products or the technology described in this document for any purpose relating to military applications or use by the military, including but not limited to the development of weapons of mass destruction. renesas electronics products and technology may not be used for or incorporated into any products or systems whose manufacture, use, or sale is prohibited under any applicable domestic or foreign laws or regulations. 6. renesas electronics has used reasonable care in preparing the information included in this document, but renesas electronics does not warrant that such information is error free. renesas electronics assumes no liability whatsoever for any damages incurred by you resulting from errors in or omissions from the information included herein. 7. renesas electronics products are classified according to the following three quality grades: "standard", "high quality", and "specific". the recommended applications for each renesas electronics product depends on the product's quality grade, as indicated below. you must check the quality grade of each renesas electronics product before using it in a particular application. you may not use any renesas electronics product for any application categorized as "specific" without the prior written consent of renesas electronics. further, you may not use any renesas electronics product for any application for which it is not intended without the prior written consent of renesas electronics. renesas electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any renesas electronics product for an application categorized as "specific" or for which the product is not intended where you have failed to obtain the prior written consent of renesas electronics. the quality grade of each renesas electronics product is "standard" unless otherwise expressly specified in a renesas electronics data sheets or data books, etc. "standard": computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "high quality": transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "specific": aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. you should use the renesas electronics products described in this document within the range specified by renesas electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas electronics shall have no liability for malfunctions or damages arising out of the use of renesas electronics products beyond such specified ranges. 9. although renesas electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. further, renesas electronics products are not subject to radiation resistance design. please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. please contact a renesas electronics sales office for details as to environmental matters such as the environmental compatibility of each renesas electronics product. please use renesas electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the eu rohs directive. renesas electronics assumes no liability for damages or losses occurring as a result of your noncompliance with applicable laws and regulations. 11. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written consent of renesas electronics. 12. please contact a renesas electronics sales office if you have any questions regarding the information contained in this document or renesas electronics products, or if you have any other inquiries. (note 1) "renesas electronics" as used in this document means renesas electronics corporation and also includes its majority-owned subsidiaries. (note 2) "renesas electronics product(s)" means any product developed or manufactured by or for renesas electronics. http://www.renesas.com refer to "http://www.renesas.com/" for the latest and detailed information. renesas electronics america inc. 2880 scott boulevard santa clara, ca 95050-2554, u.s.a. tel: +1-408-588-6000, fax: +1-408-588-6130 renesas electronics canada limited 1101 nicholson road, newmarket, ontario l3y 9c3, canada tel: +1-905-898-5441, fax: +1-905-898-3220 renesas electronics europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k tel: +44-1628-585-100, fax: +44-1628-585-900 renesas electronics europe gmbh arcadiastrasse 10, 40472 dsseldorf, germany tel: +49-211-65030, fax: +49-211-6503-1327 renesas electronics (china) co., ltd. 7th floor, quantum plaza, no.27 zhichunlu haidian district, beijing 100083, p.r.china tel: +86-10-8235-1155, fax: +86-10-8235-7679 renesas electronics (shanghai) co., ltd. unit 204, 205, azia center, no.1233 lujiazui ring rd., pudong district, shanghai 200120, china tel: +86-21-5877-1818, fax: +86-21-6887-7858 / -7898 renesas electronics hong kong limited unit 1601-1613, 16/f., tower 2, grand century place, 193 prince edward road west, mongkok, kowloon, hong kong tel: +852-2886-9318, fax: +852 2886-9022/9044 renesas electronics taiwan co., ltd. 13f, no. 363, fu shing north road, taipei, taiwan tel: +886-2-8175-9600, fax: +886 2-8175-9670 renesas electronics singapore pte. ltd. 1 harbourfront avenue, #06-10, keppel bay tower, singapore 098632 tel: +65-6213-0200, fax: +65-6278-8001 renesas electronics malaysia sdn.bhd. unit 906, block b, menara amcorp, amcorp trade centre, no. 18, jln persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: +60-3-7955-9390, fax: +60-3-7955-9510 renesas electronics korea co., ltd. 11f., samik lavied' or bldg., 720-2 yeoksam-dong, kangnam-ku, seoul 135-080, korea tel: +82-2-558-3737, fax: +82-2-558-5141 sales offices ? 2012 renesas electronics corporation. all rights reserved. colophon 1.1

▲Up To Search▲

Price & Availability of R1EX25008ASA00G

	To Download R1EX25008ASA00G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .